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87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 1 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator g eneral d escription the ics87354i is a high performance 4/5 differential-to-3.3v lvpecl clock generator and a member of the hiperclocks? family of high performance clock solutions from ics. the clk, nclk pair can accept most standard differ- ential input levels. the ics87354i is characterized to operate from a 3.3v power supply. guaranteed output and part-to- part skew characteristics make the ics87354i ideal for those clock distribution applications demanding well defined per- formance and repeatability. f eatures ? one differential 3.3v lvpecl output ? one clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum clock input frequency: 1ghz ? translates any single ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? part-to-part skew: 300ps (maximum) ? propagation delay: 2.1ns (maximum) ? lvpecl mode operating voltage supply range: v cc = 3.0v to 3.465v, v ee = 0v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs compliant packages b lock d iagram p in a ssignment ics87354i 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view clk nclk mr f_sel 1 2 3 4 hiperclocks? ic s vcc q nq v ee 8 7 6 5 q nq clk nclk 4 mr 5 r 0 1 f_sel
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 2 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 2k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 3r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a t u p t u o d e t r e v n i e h t d n a w o l o g o t ) q ( t u p t u o e u r t e h t g n i s u a c t e s e r t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t ) q n ( . 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a 4l e s _ ft u p n in w o d l l u p . 3 e l b a t n i d e b i r c s e d s a s t u p t u o q n , q r o f e u l a v r e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5v e e r e w o p. n i p y l p p u s e v i t a g e n 7 , 6q , q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 3. f unction t able r ml e s _ fe u l a v e d i v i d 1x h g i h t u p t u o q n , w o l t u p t u o q : t e s e r 00 4 01 5 f igure 1. t iming d iagram t rr clk mr q
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 3 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator t able 4a. p ower s upply dc c haracteristics , v cc = 3.0v to 3.465v, v ee = 0, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v cc = 3.0v to 3.465v, v ee = 0, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 0 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 4 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv c c v = n i v 5 6 4 . 3 =0 5 1a k l c nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n il e s _ f , r mv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n il e s _ f , r mv c c v , v 5 6 4 . 3 = n i v 0 =5 -a t able 4b. lvcmos/lvttl dc c haracteristics , v cc = 3.0v to 3.465v, v ee = 0, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 4 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator t able 5. ac c haracteristics , v cc = 3.0v to 3.465v, v ee = 0, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f k l c y c n e u q e r f t u p n i k c o l c 1z h g t d p ; y a l e d n o i t a g a p o r p 1 e t o n ) f i d ( q o t k l c7 . 11 . 2s n t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 0 0 3s p t r r e m i t y r e v o c e r t e s e r 0 0 4s p t w p m u m i n i m h t d i w e s l u p t u p n i k l c0 5 5s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 6s p c d oe l c y c y t u d t u p t u o 8 42 5% . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n t able 4d. lvpecl dc c haracteristics , v cc = 3.0v to 3.465v, v ee = 0, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 -
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 5 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator p arameter m easurement i nformation o utput r ise /f all t ime d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v t pd -1.0v to -1.465v clock outputs 20% 80% 80% 20% t r t f v sw i n g v cmr cross points v pp v cc v ee clk nclk clk nclk q nq t sk(pp) nqx qx nqy qy part 1 part 2 p art - to -p art s kew p ropagation d elay v cc v ee o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% q nq
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 6 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput p ins
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 7 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 2a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 8 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utput f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 9 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics87354i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics87354i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 104ma = 360mw ? power (outputs) max = 3.465mw/loaded output pair total power _max (3.465v, with all outputs switching) = 360mw + 30mw = 390mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.390w * 103.3c/w = 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 6. t hermal r esistance ja for 8- pin soic, f orced c onvection 0 200 500 single-layer pcb, jedec standard t est boards 1 53.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard t est boards 1 12.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 10 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 11 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ics87354i is: 1745 t able 6. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 12 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator p ackage o utline - m s uffix for 8 l ead soic t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 13 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i m a 4 5 3 7 8 s c ii m a 4 5 3 7 8c i o s d a e l 8e b u tc 5 8 o t c 0 4 - t i m a 4 5 3 7 8 s c ii m a 4 5 3 7 8c i o s d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i m a 4 5 3 7 8 s c il i a 4 5 3 7 8c i o s " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i m a 4 5 3 7 8 s c il i a 4 5 3 7 8c i o s " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.
87354ami www.icst.com/products/hiperclocks.html rev. a may 22, 2006 14 integrated circuit systems, inc. ics87354i 4/5 d ifferential - to - 3.3v lvpecl c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 t2 . q n o t q n , q m o r f 7 & 6 s n i p d e t c e r r o c - n o i t p i r c s e d n i p d e d d a . s n i p t u p n i d e s u n u r o f s n o i t a d n e m m o c e r 6 0 / 2 2 / 5

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